Direct Memory Access

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Direct Memory Access

Direct Memory Access (DMA) is a technique that permits an input or output (I/O) device to receive or send data directly to or from the primary memory, detouring the CPU to speed up memory operations. A DMA controller (DMAC) is a chip which is used to manage the process.

Just before start an I/O operation, the device driver loads the suitable registers with-in the device controller.
■ The controller starts the transmission of data from the device to its local buffer, Once the transmission of data is complete, the device controller report to the device driver via an interrupt that it has done its operation.
■ This procedure of interrupt-driven I/O is sufficient for moving small amounts of data however can produce high overhead when used for bulk data movement for example disk I/O.
■ Direct memory access (DMA) is used to solve this problem.
■ Device controller transfers chunks of data from buffer storage directly to main memory without CPU interference.
■ Only a single interrupt is created per block, instead of the one interrupt per byte.

Structure of direct access memory is given as:

Direct Memory Access

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In older computers 4 DMA channels were numbered as 0, 1, 2 and 3 when the 16-bit industry standard architecture (ISA) introduced the expansion bus with additional channels 5, 6 and 7. ISA was a computer bus standard for IBM– compatible computers, permitting a device to initiate transactions bus mastering at faster speed. Each and every DMA transfers around 2 MB of data per second. Communication between hardware and software the computer’s resource tools are used. There are four following types of system resources:

  • I/O addresses
  • Memory addresses
  • Interrupt request numbers (IRQ)
  • DMA channels

DMA channels are used to communicate data b/w the external device and the system memory. All these four system resources depend on certain lines on a bus. Some lines on the bus are used for DMA channels and some for IRQs and some for addresses the I/O addresses and the memory address. A DMA channel allows a device to transfer data without revealing the CPU to a work overload. The CPU copies every single piece of data using a peripheral-bus from the I/O device without the DMA channels. Using a peripheral-bus which occupies the CPU during the read/write process and does not permit other work to be performed till the operation is accomplished.

The CPU can execute other tasks with DMA while data transfer is being performed. The first initiated of the CPU is transfer of data. During the transfer of data between the I/O device and DMA channel the CPU accomplishes other tasks. The CPU receives an interrupt request from the DMA controller, when the data transfer is completed.

 

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